Multi-level cell (MLC) 

Introduction

Over the years, advancements in process technology have led to significant improvements in flash memory. Since its introduction in 1988, the cost per Mbyte has decreased and the density has increased thanks to process innovation. For instance, Intel’s first flash device in 1988 was a 256Kb device priced at $20 ($640 per Mbyte). However, by 1996, an 8 Mbit device was available for just $12 ($12 per Mbyte), representing a remarkable reduction in cost per Mbyte by more than 50 times.

To further enhance density and reduce costs, a concept called MultiLevel Cell (MLC) technology was developed. This innovation involves storing multiple bits of information on a single memory transistor. By storing two bits per memory cell, we can instantly double the density within the same space and bring down the cost per Mbyte. With continued process scaling and the implementation of MLC technology, it is expected that flash memory will reach a price point of $1 per Mbyte by 2001.

The growing demand for non volatile code or data storage from various applications necessitates higher density flash products at increasingly lower costs.

The process of scaling in the flash industry has made significant advancements over the past 8 years. Initially, we had devices with a capacity of 256Kb priced at $640 per Mbyte, but now we have devices with an 8Mb capacity priced at only $12 per Mbyte. This trend of continuous innovation is expected to continue, leading to further increases in density and reductions in cost per Mbyte. One method that contributes to this progress is MultiLevel Cell technology, which allows multiple bits of information to be stored on a single memory transistor. This results in a higher number of bits stored per area, ultimately leading to more cost effective storage solutions.

MLC structure

MLC Cell Operations

In order for MLC devices to function properly, they need to handle electrical charge with great precision. Specifically, these devices should be able to accurately place, sense and store charge over time. The NOR architecture addresses these requirements by directly connecting each memory cell’s gate, source and drain. Each individual cell consists of a single transistor that is directly linked to the necessary control voltages, ensuring precise manipulation of the charge.

MLC Program Operation

During the programming process, it is crucial to carefully apply a specific amount of charge onto the floating gate. The analog voltage across each flash cell is divided into different Vt levels based on the number of electrons present on the floating gate. This charge placement is controlled through Channel Hot Electron (CHE) injection.

To achieve accurate charge placement during programming, each cell’s ground connection, bitline connection and wordline connection play a vital role. The control gate of a cell is connected to the internally generated supply voltage through a direct wordline link and row decoding mechanism. The drain receives constant voltage pulses via a direct bitline connection and column decoding. The source is directly connected to ground.

The presence of stored electrons on the floating gate establishes a potential that needs to be overcome by the control gate.

This could lead to a higher voltage requirement for turning on the transistor (memory cell). It is crucial to have accurate control over the gate and drain for proper placement of MLC memory cells.

MLC Read Operation

During the process of reading data, it is crucial to accurately sense the charge. This is achieved by establishing direct connections with each memory cell. The purpose of the data read operation is to quickly and reliably determine the level of each memory cell. The speed at which this operation is performed is comparable to technology that stores only one bit per cell.

To determine which of the four levels a memory cell falls within, the data read operation analyzes the threshold voltages of three reference cells. These reference cells are biased in a way that allows them to conduct a current proportional to their specific voltage threshold (Vt). During the read operation, VREAD is applied to the control gate, while the source is grounded and a drain bias is applied. In this mode, a memory cell conducts a current (ICell) that corresponds to its own voltage threshold.

When cells are biased in this manner, there exists an inverse relationship between the current conducted through each cell and its voltage threshold. Therefore, if the current passing through a flash array cell exceeds a certain reference current (ICell > I R#Ref), it indicates that its voltage threshold (VtCell) is lower than that of the reference cell (VtRef). The data stored in memory cells can be read by comparing their currents with those passing through three reference cells.

To perform a read operation, the current flowing through the memory cell’s bitline is compared to the current generated by three read reference circuits. This current is detected by connecting the drain to an active load, which in turn is connected to a differential sense amplifier.

Additional FAQ

1.What are examples of data structures with multiple levels?

Multiple levels of structures and classifications are used to organize data in various contexts. For instance, if we consider a multilevel data structure for students within schools, the students can be seen as a random sample from a larger population of students, just as the schools represent a random sample from a broader population of schools. It’s important to note that variables like gender and social class should not be considered as levels themselves.

2.What does multi level cell SSD refer to?

An MLC SSD (Solid State Drive), traditionally defined, is an SSD that can store two bits of data per cell. If an SSD is capable of storing more than two bits per cell, it would not be categorized as MLC. On the other hand, if it can store three bits of data per cell, it would be classified as TLC.

3.How can multi level data sorting be performed in Excel?

To perform multi level data sorting in Excel, you can arrange the information in more than one column either in ascending or descending order.

4.What are multilevel or mixed models?

Multilevel modeling focuses on designs where all the random factors are nested within each other—for example, children nested within classes, which are nested within schools that further nest within districts. These nesting structures are commonly referred to as ‘levels.’In statistical modeling, these factors could be referred to as “random variables.”